Fundamental of Computer Applications Quadrillion Redundancies

Question: Discuss about the Fundamental of Computer Applications for Quadrillion Redundancies. Answer: 1 (A) Hexadecimal The ASCII representation of +15.3682 in hexadecimal is 2B 31 35 2E 33 36 38 32. (B) Binary The ASCII representation of +15.3682 in binary is 00101011 00110001 00110101 00101110 00110011 00110110 00111000 00110010. (C) Octal The ASCII representation of +15.3682 in Octal is 53 61 65 56 63 66 70 62. (D) Decimal The ASCII representation of +15.3682 in decimal is 43 49 53 46 51 54 56 50. 2. (A) Representation in IEEE 754 floating-point format The given decimal number is +88.875. Let set the sign bit to 0, because it is a positive number. Now, Convert 88.875 to binary (88.875)10 = (01011000)2. Bits 30 23 exponent field is 10000101 Decimal value of exponent field and exponent 133 -127 =6. Bits 22 0 Significand is1 .01100011100000000000000 Decimal value of the significand 1.3886719 The final hexadecimal value is 42B1C000 (B) Hypothetical floating-point format The given decimal number is +88.875. This is a positive number, so set the sign bit 0. Now covert the decimal number 88.875 in binary: Now, 88.875 = (0. 10110000111)*27; Let, 10110000111 is 11 bit number and the mantissa (25-11) = 14. Adding 14 zero to the mantissa: 1011000011100000000000000 The exponent is: 31+11 = 42, that equals 00101010. Therefore, the binary number is 0001010101011000011100000000000000. The hexadecimal number is 5561C000. Bibliography Anderson, J. A. (2014). Trans-floating-point arithmetic removes nine quadrillion redundancies from 64-bit ieee 754 floating-point arithmetic. Brain, M., Tinelli, C., Rmmer, P., Wahl, T. (2015, June). An automatable formal semantics for IEEE-754 floating-point arithmetic. In Computer Arithmetic (ARITH), 2015 IEEE 22nd Symposium on (pp. 160-167). IEEE. Chen, D., Eisley, N. A., Heidelberger, P., Steinmacher-Burow, B. (2015). U.S. Patent No. 8,977,669. Washington, DC: U.S. Patent and Trademark Office. Cowlishaw, M. F., Mueller, S. M., Schwarz, E., Yeh, P. C. (2016). U.S. Patent No. 9,244,654. Washington, DC: U.S. Patent and Trademark Office. Garg, H., Khandelwal, K. K., Gupta, M., Agrawal, S. (2014, April). Uniform selection of vertices for watermark embedding in 3-d polygon mesh using ieee754 floating point representation. In Communication Systems and Network Technologies (CSNT), 2014 Fourth International Conference on (pp. 788-792). IEEE. Persohn, K. J., Povinelli, R. J. (2012). Analyzing logistic map pseudorandom number generators for periodicity induced by finite precision floating-point representation. Chaos, Solitons Fractals, 45(3), 238-245. Ramesh, A. P., Tilak, A. V. N., Prasad, A. M. (2013, January). An FPGA based high speed IEEE-754 double precision floating point multiplier using Verilog. In Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT), 2013 International Conference on (pp. 1-5). IEEE. Salehi, S., DeMara, R. F. (2015, April). Energy and Area Analysis of a Floating-Point Unit in 15nm CMOS Process Technology. In SoutheastCon 2015 (pp. 1-5). IEEE.